IMPORTANT Warning : I have not tested this idea, but I post it here. I am not liable for any damages. You do anything on your own risk
Surfing the Net about SPI port on my MB have found a very curious post.
In the comments it was discussed that it is possible to connect an additional flash chip t mb.
1 SPI memory has 8 pins. We are especially interested in 2 ones:
CS# and HOLD#.
Signal I/O Description
SO - data output.
SI - data input.
SCK - clock.
#CS - Chip select. Active chip must have it pulled down, all other chips must have it pulled up.
#HOLD - when pulled down (falling edge) , stops any communication and waits for rising edge. Beetween it the state is stored.
#W - protects the memory area specified by Status Register bits BP2:BP0 when pulled down.
V_CC - power.
GND - ground.
SPI chips can be connected parallelily, active chip is selected using CS.
Some MB has an SPI port connected to pins of the memory chip. You can buy additional SPI microschemes and create a PCB of such design:
![[Image: B4m7pwF.png]]()
In the top is JSPI1 connector of mb where #HOLD of chip on MB (the most left pin of connector on the picture) is grounded (it seems we need to put here a resistor to prevent shortcut).
The memory chips on PCB are connected to SPI, and upper chip is selected.
#CS of JSPI1 is already grounded because main system bios is already selected, but groundring #HOLD we disabled it and can use the enabled chip on PCB instead of it.
Surfing the Net about SPI port on my MB have found a very curious post.
In the comments it was discussed that it is possible to connect an additional flash chip t mb.
1 SPI memory has 8 pins. We are especially interested in 2 ones:
CS# and HOLD#.
Signal I/O Description
SO - data output.
SI - data input.
SCK - clock.
#CS - Chip select. Active chip must have it pulled down, all other chips must have it pulled up.
#HOLD - when pulled down (falling edge) , stops any communication and waits for rising edge. Beetween it the state is stored.
#W - protects the memory area specified by Status Register bits BP2:BP0 when pulled down.
V_CC - power.
GND - ground.
SPI chips can be connected parallelily, active chip is selected using CS.
Some MB has an SPI port connected to pins of the memory chip. You can buy additional SPI microschemes and create a PCB of such design:
![[Image: B4m7pwF.png]](http://i.imgur.com/B4m7pwF.png)
In the top is JSPI1 connector of mb where #HOLD of chip on MB (the most left pin of connector on the picture) is grounded (it seems we need to put here a resistor to prevent shortcut).
The memory chips on PCB are connected to SPI, and upper chip is selected.
#CS of JSPI1 is already grounded because main system bios is already selected, but groundring #HOLD we disabled it and can use the enabled chip on PCB instead of it.